Field of Use
The present invention relates to multilayer printed circuit boards and more particularly to the construction of multilayer printed circuit boards using surface mount technology.
Prior Art
The processes for producing complex multilayer printed circuit boards are well known in the art. An example is disclosed in U.S. Pat. No. 4,495,479.
In such multilayer printed circuit boards, the IC components in various dual in-line packages are set into holes drilled into the boards and soldered to signal conductors on different layers through the plated through holes. Various techniques, including fine line technology, have been used for increasing the number of lines or connections per square inch. However, this results in cost increases. Furthermore, there are limitations on the number of components which can be mounted on the board surface because of the spacing requirements between components and hole sizes.
The advent of surface mount technology allows IC components to be soldered to pads which are on the board's surface. Because surface mounted component packages are smaller than DIPs and do not require large holes for mounting, more such components can be mounted on the surface of the board. This results in increased board density. Since the components are mounted on the surface of the board, surface mount technology also permits IC components to be mounted on both sides of the board.
While surface mount technology allows for greater flexibility in circuit boards, it becomes difficult to provide the proper interconnection between such components when they are mounted on both sides of the board. Furthermore, because of the greater such density of components on boards, testing is complicated due to the increase in the number of leads. This can give rise to new test equipment requirements, resulting in cost increases.
Accordingly, it is a primary object of the present invention to provide a multilayer printed circuit board design which uses surface mount technology without a substantial increase in board layout complexity.
It is a further object of the present invention to provide a multilayer printed circuit board design which uses surface mount technology and is compatible with standardized testing equipment.